Agilex™ 3 FPGAs and SoCs Device Data Sheet

ID 848370
Date 8/11/2025
Public
Document Table of Contents

Avalon® Streaming Configuration Timing

Table 99.   Avalon® Streaming Timing Parameters for ×8 and ×16 Configurations For specification status, see the Data Sheet Status table
Symbol Description Minimum Unit
tACLKH AVST_CLK high time 3.6 ns
tACLKL AVST_CLK low time 3.6 ns
tACLKP AVST_CLK period 8 ns
tADSU 138 AVST_DATA setup time before rising edge of AVST_CLK 2.1 ns
tADH 138 AVST_DATA hold time after rising edge of AVST_CLK 0.1 ns
tAVSU AVST_VALID setup time before rising edge of AVST_CLK 2.1 ns
tAVDH AVST_VALID hold time after rising edge of AVST_CLK 0 ns
Figure 51.  Avalon® Streaming Configuration Timing Diagram
138 Data sampled by the FPGA (sink) at the next rising clock edge.