Agilex™ 3 FPGAs and SoCs Device Data Sheet

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ID 848370
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 3 FPGAs and SoCs Device Data Sheet
Agilex™ 3 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 3 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 3 FPGAs and SoCs Device Data Sheet

Document Revision History for the Agilex 3 FPGAs and SoCs Device Data Sheet

Document Version Changes
2025.08.11
  • Updated the specifications for TCK clock frequency (FJCP) and TCK clock period (tJCP) in the HPS JTAG Timing Requirements table.
  • Added description to the System PLL Reference Clock (Using HVIO) Specifications table.
  • Added Insertion Loss specification to the Receiver Electrical Specifications table.
  • Added Input clock or external feedback clock input duty cycle (tEINDUTY) parameter in the I/O PLL Specifications table.
  • Updated the maximum specifications for Input clock frequency source (-6S and -7S) in the I/O PLL Specifications table.
  • Updated the bit stream sizes for the variants in the Configuration Bit Stream Sizes table.
  • Revised the HPS and SDM DC Characteristics and HPS and SDM I/O Standard Specifications, organizing them into individual sections:
    • HPS I/O DC Characteristics
    • SDM I/O DC Characteristics
    • HPS I/O Standard Specifications
    • SDM I/O Standard Specifications
  • Updated the maximum specifications for Clock Frequency fHSCLK_in(input clock frequency) SLVS400 I/O Standards in the Agilex 3 FPGAs LVDS SERDES Specifications table.
  • Updated the specifications in the Programmable IOE Delay Specifications table.
  • Updated the conditions of Tri-stated pin to VO in the HVIO Pin Leakage Current table.
  • Added footnote about receiver compliance to the VOH in the MIPI D-PHY Low-Power I/O Standards Specifications table.
  • Updated the HDMI 2.1 Lane rate specifications in the Electrical Compliance List table.
  • Updated the fixed point multiplication modes specifications in the Agilex 3 FPGAs DSP Block Performance Specifications for Single DSP Block and Agilex 3 FPGAs DSP Block Performance Specifications for Multiple DSP Blocks tables
  • Updated the MLAB and M20K block memory specifications (-6S and -7S) in the Agilex 3 FPGAs Memory Block Performance Specifications table.
2025.04.28 Initial release.
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