Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 4/07/2025
Public

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2.2.13.3. Static Phase Error Calibration

In Agilex™ 3 devices, a static phase error calibration is initiated after power up calibration. This is done automatically to reduce the phase error between reference clock and feedback clocks.