Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 4/07/2025
Public

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6.2.2. Setting Up the EMIF Calibration FPGA IP

Figure 26.  EMIF Calibration IP

Set the following parameters:

  • INSTANCE_ID: 0
  • Number of Peripheral IPs: 0
  • Number of standalone I/O PLLs: 1
  • AXI-L Subordinate Port Mode: Connect to Fabric.