Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 4/07/2025
Public

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4. Clock Control Altera™ FPGA IP Core

The Clock Control Altera™ FPGA IP provides clock control features such as enabling entry to the clock network, clock multiplexing, clock gating, and clock division for the Agilex™ 3 devices.

The Clock Control IP is available under the Basic Functions > Clocks: PLLs and Resets category of the IP Catalog.