Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

Download PDF
ID 847921
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 Clocking and PLL Overview 2. Agilex™ 3 Clocking and PLL Architecture and Features 3. Agilex™ 3 Clocking and PLL Design Considerations 4. Clock Control Altera™ FPGA IP Core 5. IOPLL FPGA IP 6. I/O PLL Reconfiguration 7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration
3. Agilex™ 3 Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES IP
4. Clock Control Altera™ FPGA IP Core x
4.1. Release Information for Clock Control Altera™ FPGA IP 4.2. Clock Control Altera™ FPGA IP Parameters 4.3. Clock Control Altera™ FPGA IP Ports and Signals
5. IOPLL FPGA IP x
5.1. Release Information for IOPLL FPGA IP 5.2. IOPLL FPGA IP Parameters 5.3. IOPLL IP Ports and Signals
5.2. IOPLL FPGA IP Parameters x
5.2.1. IOPLL IP Parameters - PLL Tab 5.2.2. IOPLL IP Parameters - Settings Tab 5.2.3. IOPLL IP Parameters - Cascading Tab 5.2.4. IOPLL IP Parameters - Advanced Parameters Tab
6. I/O PLL Reconfiguration x
6.1. Release Information for EMIF Calibration FPGA IP 6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP 6.3. Implementing HVIO I/O PLL Reconfiguration 6.4. Reconfiguration Guideline for I/O PLLs 6.5. Axilite Interface Ports in the EMIF Calibration IP 6.6. Address Bus and Data Bus Settings
6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP x
6.2.1. Setting Up the IOPLL FPGA IP 6.2.2. Setting Up the EMIF Calibration FPGA IP 6.2.3. Connectivity Between IOPLL FPGA IP and EMIF Calibration IP
6.3. Implementing HVIO I/O PLL Reconfiguration x
6.3.1. Setting Up the IOPLL FPGA IP 6.3.2. Read and Write Operations
6.4. Reconfiguration Guideline for I/O PLLs x
6.4.1. Enabling Reconfiguration for The Desired I/O PLL 6.4.2. Clearing off Calibration Statuses 6.4.3. Reconfiguring The I/O PLL 6.4.4. Recalibration of I/O PLL 6.4.5. Clock Gating (Optional)
6.6. Address Bus and Data Bus Settings x
6.6.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration 6.6.2. Data Bus Setting for Clock Gating Reconfiguration 6.6.3. Data Bus Setting For Charge Pump Current
1. Agilex™ 3 Clocking and PLL Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features
3. Agilex™ 3 Clocking and PLL Design Considerations
4. Clock Control Altera™ FPGA IP Core
5. IOPLL FPGA IP
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

6. I/O PLL Reconfiguration

You can use Agilex™ 3 devices to implement phase-locked loop (PLL) reconfiguration and dynamic phase shift for I/O PLLs.

The Agilex™ 3 I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure the I/O PLL settings in real-time. You can change the divide settings of the PLL without the need to reconfigure the entire FPGA. The Agilex™ 3 I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.

For HSIO I/O PLLs, you can reconfigure the divide settings via AXI4-Lite interfaces within the EMIF Calibration IP. For I/O PLLs in the HVIO blocks, you can directly reconfigure the divide settings by accessing the reconfiguration ports.

You can use the feature as follows:

  • I/O PLL Reconfiguration
    • Enable dynamic reconfiguration of PLL the dynamic reconfiguration tab of the IOPLL FPGA IP to reconfigure the individual I/O PLL registers. You can also perform dynamic phase shift.
  • Recalibration of the I/O PLL
    • Perform recalibration of the I/O PLL without any reconfiguration.
    • Trigger recalibration if the reference clock frequency changes.
  • I/O PLL clock gating
    • Gate and un-gate I/O PLL output clock 0 to output clock 6 of the I/O PLL.

Section Content
Release Information for EMIF Calibration FPGA IP
Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP
Implementing HVIO I/O PLL Reconfiguration
Reconfiguration Guideline for I/O PLLs
Axilite Interface Ports in the EMIF Calibration IP
Address Bus and Data Bus Settings

Level Two Title