Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 4/07/2025
Public

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3.6. IP Constraints

To implement the IOPLL IP, you must adhere to the following constraints:

  • Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP.
  • Altera recommends reading the SDC for all I/O PLLs first in a design. You can do this by listing the IP before others in the .qsf file.