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1. Agilex™ 3 Clocking and PLL Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features
3. Agilex™ 3 Clocking and PLL Design Considerations
4. Clock Control Altera™ FPGA IP Core
5. IOPLL FPGA IP
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
6.1. Release Information for EMIF Calibration FPGA IP
6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP
6.3. Implementing HVIO I/O PLL Reconfiguration
6.4. Reconfiguration Guideline for I/O PLLs
6.5. Axilite Interface Ports in the EMIF Calibration IP
6.6. Address Bus and Data Bus Settings
5. IOPLL FPGA IP
The IOPLL FPGA IP allows you to configure the settings of the Agilex™ 3 I/O PLL.
The IOPLL IP supports the following features:
- Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
- Generates up to four output clocks for I/O bank I/O PLL and seven output clocks for fabric-feeding I/O PLL for the Agilex™ 3 device.
- Switches between two reference input clocks.
- Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL dedicated cascading mode.
The IOPLL IP is available under the Basic Functions > PLL category of the IP Catalog.