Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 4/07/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1.1. Clock Network Architecture

Each Agilex™ 3 device is divided into a number of evenly sized clock sectors.

Clock Sector in an Agilex™ 3 devices is implemented as an array of sectors. The following figure shows the clock sector example of 5 rows, and 6 columns. I/O banks are at the top and bottom of the Agilex™ 3 devices.
Figure 1. Clock Sector Floorplan for Agilex™ 3 Devices