GTS AXI Multichannel DMA IP for PCI Express* User Guide
5.1.2. AXI-S Packet Generate/Check Design Example
Below is the block diagram of the packet generator design example with a single-port AXI Streaming interface supporting multiple channels without any interleaving. In the H2D direction, the design example checks for the received packets and software, then reads the status registers to make sure there are no errors. In the D2H direction, the design example generates the packets and forwards them to the host side by means of a PCIe MWr.
Additionally, the design example enables the AXI-Lite PIO master, which bypasses the DMA path. This allows the application running in the host to perform single, non-bursting register read/write operations with the on-chip memory block.
The AXI-S Packet Generate/Check design example includes the following components:
| Design Components | Descriptions |
|---|---|
| GTS AXI Streaming FPGA IP for PCI Express | Incorporate PCI Express (PCIe*) into your design utilizing an advanced PCIe hardened protocol stack, which encompasses the transaction, data link, and physical layers. It also includes optional components like Single Root I/O Virtualization (SR-IOV) for virtualization applications that demand high-bandwidth data transfer to and from the host memory. This component converts the PCIe serial link transfer to the AXI Stream interface and directs the TLP data received to the GTS AXI Multichannel DMA IP. |
| GTS AXI Multichannel DMA IP for PCI Express | Facilitates efficient data transfer between the local FPGA and the host through multiple DMA channels over the PCIe link. Each DMA channel comprises a host-to-device (H2D) and a device-to-host (D2H) queue pair, operating on descriptor-based queues established by the driver software for data transfer. It is engineered to support standalone Endpoint or Rootport functionality, offering AXI-S and AXI-MM interfaces to the user logic. |
| GTS System PLL Clocks IP | This IP is required for the PCIe interface implementation on Agilex™ 5 devices to configure the reference clock for the System PLL and provides the clock signal for p<n>_i_syspll_c0_clk of the GTS AXI Streaming IP.
Note: For more information, refer to the Implementing the GTS System PLL Clocks IP section in the GTS Transceiver PHY User Guide.
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| GTS Reset Sequencer IP | This IP must be instantiated for each Agilex™ 5 FPGA side that uses transceivers for simulation and proper device operation. It provides the PMA Control Unit clock to the i_flux_clk clock of the GTS AXI Streaming IP.
Note: For more information, refer to the Implementing the GTS Reset Sequencer IP section in the GTS Transceiver PHY User Guide.
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| Reset Release IP | This IP holds a control circuit in reset until the device has fully entered user mode. The FPGA asserts the INIT_DONE output to signal that the device is in user mode. It is required when using the GTS AXI Streaming IP.
Note: For more information on the Reset Release IP, refer to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.
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| Packet Generator and Checker for MCDMA | This module implements a packet generator for Device-to-Host (D2H) DMA operations and a packet checker for Host-to-Device (H2D) DMA operations. In addition, it provides a PIO interface, which is mapped to BAR2, that allows the application to perform single, non-bursting register read/write operations with the on-chip memory block. |
| BAR/PF/VF Interpreter for MCDMA | This module interprets the PIO address mapping to decode the physical function number, virtual function number and address of the incoming packet. |
| AXI to AVALON Adapter Bridge | This adapter module converts the AXI interface to an Avalon interface and the Avalon Interface to an AXI interface for data transfer between the GTS AXI MCDMA IP and the Packet Generator and Checker module. |
| rst_ctrl_0 | This module handles the reset and handshake signals of the GTS AXI Streaming IP for graceful entry and exit for each of the resets (cold, warm, etc.) especially when initiated by the host system. |
| IOPLL FPGA IP | This IP is required to configure the settings of the Agilex™ 5 I/O PLL to provide a 100MHz clock signal for the AXI-Lite interface in the design. |