AN 999: Drive-on-Chip with Functional Safety Design Example: Agilex™ 7 Devices

ID 823627
Date 7/04/2024
Public

Visible to Intel only — GUID: ghi1716371808107

Ixiasoft

Document Table of Contents

5.2. HPS Channel Speed Monitoring Safety Application

The Drive-On-Chip with Functional Safety design implements an HPS channel safety function with an application running in the Agilex 7 HPS. The application is by default cross compiled for ARM64 architecture and the executable is added to /opt/hpssafechannel directory during the Yocto build. The application is set to run as a service after the HPS finish booting Linux. If necessary, you can compile and modify the application without building Yocto.

The main functions of the HPS channel speed monitoring safety application are:

  • Detect and connect with the devices in the FPGA soft logic necessary to implement the Safety Function
  • Estimate speed at 25 kHz rate, accessing the drive-on-chip quadrature encoder pulse encoder raw position values.
  • Generate the HPS payload according to specification.
  • Detect overspeed in the Axis0 of the drive-on-chip hardware.
  • Cross compare the HPS payload with the FPGA payload.
  • Generate HPS channel safety outputs to the external safety logic block.
  • Write values for GUI display in the GUI safety memory.
  • Print the status of the application in the UART terminal.