AN 999: Drive-on-Chip with Functional Safety Design Example: Agilex™ 7 Devices
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Ixiasoft
Visible to Intel only — GUID: bga1716295158737
Ixiasoft
4.5. External Safety Logic
Results of payload comparison
Both the FPGA and HPS process their own comparisons to ensure both values of payload agree. The design passes these outputs into the external safety logic to ensure that both comparison checks agree
Clock Checker
The external safety logic actively takes in respective FPGA and HPS clocks as inputs of different frequencies. The design processes these signals through the clock checker to ensure frequencies are in a tolerable range.
The clock checker takes a fixed reference clock and its respective reset, and compares it to a clock under comparison. Using fixed parameterizable thresholds, the clock checker determines whether the clock under test falls into appropriate and safe frequencies. The external safety logic uses the clock checker to ensure that HPS and FPGA clocks operate at appropriate frequencies, and the design has no instances of skewing or jitter when passing through various blocks.
Channel Operation
Refers to the two heartbeat signals present in FPGA and HPS operations. These signals help to identify that everything is functional within a process safety time. The external safety logic receives these signals as inputs, which the design then delays using two flip-flops to prevent any metastable values that might fluctuate through. The design applies a window check to allow for the heartbeat to arrive within a determinable time span.
CRAM Configuration Check
Ensures that no soft errors or transient faults occur.
Power Supply Check
Ensures no failures because of loss of power or unsafe operating voltage conditions. The design checks the power supply by using the Mailbox Client with Avalon Streaming Interface IP. The design compares the voltages to optimal operating voltage conditions. Refer to Agilex 7 User Guide.
Temperature Check
Ensures no failures because of unsafe temperatures. The design checks the temperature by using the Mailbox Client with Avalon Streaming Interface IP. The design compares the temperature values against parameterizable temperature limits to ensure they are in a safe range. For more details on power supply and temperature check, refer to Agilex 7 Power Management User Guide.
Complementary Bit Package
The complementary bit package contains a typedef for a definition of type called compli which allows effective storage of complementary bit pairs. The complementary bit check also contains fault checking functions to ensure that received complementary pairs are organized into the correct format.
The design processes external safety logic's I/O in a complementary manner to detect any stuck bits during transmissions. To accommodate any timing delays, complementary pairs can arrive within a preset and adjustable window.