AN 1007: Partial Reconfiguration Design Simulation Tutorial

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ID 819958
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration Design Simulation Tutorial Introduction 2. Partial Reconfiguration Simulation Overview 3. Partial Reconfiguration Simulation Capabilities 4. Types of Verification Achievable Through Simulation 5. Partial Reconfiguration Simulation Requirements 6. Partial Reconfiguration Simulation Reference Design Requirements 7. Partial Reconfiguration Simulation Reference Design Overview 8. Partial Reconfiguration Simulation Reference Design Files 9. PR Simulation Reference Design Walkthrough 10. PR Simulation Results 11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial
9. PR Simulation Reference Design Walkthrough x
9.1. Step 1: Getting Started 9.2. Step 2: Creating a Project Revision for PR Simulation 9.3. Step 3: Adding RTL Design Files to the pr_sim Revision 9.4. Step 4: Adding PR Simulation Design Files to the pr_sim Revision 9.5. Step 5: Generating Gate-level PR Simulation Models for the Persona 9.6. Step 6: Preparing the Setup Simulation Script 9.7. Step 7: Run PR Simulation
10. PR Simulation Results x
10.1. Persona Swapping Simulation 10.2. Reset Sequence Simulation 10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL
1. Partial Reconfiguration Design Simulation Tutorial Introduction
2. Partial Reconfiguration Simulation Overview
3. Partial Reconfiguration Simulation Capabilities
4. Types of Verification Achievable Through Simulation
5. Partial Reconfiguration Simulation Requirements
6. Partial Reconfiguration Simulation Reference Design Requirements
7. Partial Reconfiguration Simulation Reference Design Overview
8. Partial Reconfiguration Simulation Reference Design Files
9. PR Simulation Reference Design Walkthrough
10. PR Simulation Results
11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial

10. PR Simulation Results

By looking at the Simulation waveforms, you can verify whether the signals behave consistently with your expectations. The simulation in this tutorial works as follows:
  1. The simulation logic in the testbench top_tb drives the pr_activate, persona_select and freeze signals.
  2. The testbench triggers a PR transition by asserting the pr_activate signal.
  3. The persona_select signal selects the current persona. In addition, it also controls the PR input and output multiplexer select input lines to control the correct input and output of the persona.
  4. The pr_activate signal forces the output of the PR output multiplexer to unknown (X) values (for freeze logic verification). In addition, it also triggers the PR simulation register model to show unknown (X) value in all registers of the persona (for reset sequence verification).
  5. The freeze signal freezes the PR region output and sets to known value while the PR transition is occurring.
  6. After some time transpires, the testbench de-asserts pr_activate signals and resets the PR persona.
The simulation of top_sim module is separated into the following sections:
  • Initialization
  • Initial Reset
  • Section #1: PR with Freeze, then reset (PR W/ FRZ → RST)
  • Section Reset
  • Section #2: PR, then Reset (PR → RST)
  • Section Reset
  • Section #3: PR Only (PR ONLY)
Figure 12. Simulation Waveform

Section Content
Persona Swapping Simulation
Reset Sequence Simulation
Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL

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