AN 1007: Partial Reconfiguration Design Simulation Tutorial

Download PDF
ID 819958
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration Design Simulation Tutorial Introduction 2. Partial Reconfiguration Simulation Overview 3. Partial Reconfiguration Simulation Capabilities 4. Types of Verification Achievable Through Simulation 5. Partial Reconfiguration Simulation Requirements 6. Partial Reconfiguration Simulation Reference Design Requirements 7. Partial Reconfiguration Simulation Reference Design Overview 8. Partial Reconfiguration Simulation Reference Design Files 9. PR Simulation Reference Design Walkthrough 10. PR Simulation Results 11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial
9. PR Simulation Reference Design Walkthrough x
9.1. Step 1: Getting Started 9.2. Step 2: Creating a Project Revision for PR Simulation 9.3. Step 3: Adding RTL Design Files to the pr_sim Revision 9.4. Step 4: Adding PR Simulation Design Files to the pr_sim Revision 9.5. Step 5: Generating Gate-level PR Simulation Models for the Persona 9.6. Step 6: Preparing the Setup Simulation Script 9.7. Step 7: Run PR Simulation
10. PR Simulation Results x
10.1. Persona Swapping Simulation 10.2. Reset Sequence Simulation 10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL
1. Partial Reconfiguration Design Simulation Tutorial Introduction
2. Partial Reconfiguration Simulation Overview
3. Partial Reconfiguration Simulation Capabilities
4. Types of Verification Achievable Through Simulation
5. Partial Reconfiguration Simulation Requirements
6. Partial Reconfiguration Simulation Reference Design Requirements
7. Partial Reconfiguration Simulation Reference Design Overview
8. Partial Reconfiguration Simulation Reference Design Files
9. PR Simulation Reference Design Walkthrough
10. PR Simulation Results
11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial

10.2. Reset Sequence Simulation

Reset sequence simulation verifies that persona functions start correctly after PR has completed. It can be done in the context of the whole design or as a block level simulation of just the persona. This simulation requires the post-synthesis gate-level PR simulation model of the persona. During the time when a PR operation occurs, you drive the pr_activate signal to set unknown (X) values into all registers inside the persona. After PR, the registers require to be explicitly reset to a known state.

The testbench sequence to run this simulation consists of the following:

  • Assert the pr_activate signal.
  • After completing PR, deassert the pr_activate signal.
  • Reset the persona.

The simulation steps are as follows:

  1. Section reset occurs over two cycles to reset the persona to the default AND gate persona and reset the persona to a known state to ensure proper initial functionality.
  2. Simulation transitions to Section #2: PR, then reset.
  3. The persona transition sequence occurs. However, during this PR transition, the freeze signal does not assert. As a result, the output is undefined (as X) during this time until the reset is asserted to reset the output and the persona to a known state. This undefined output is a feature of the post-synthesis gate-level PR simulation model to output an undefined value during PR transitions.
    Figure 14. Reset Sequence Simulation Waveform: Persona Registers Reset to a Known State
  4. Section Reset occurs again over two cycles to ensure the correct initial functionality. The simulation proceeds through the AND gate persona as expected.
  5. Simulation transitions to Section #3: PR Only.
  6. Once the PR transition occurs and completes the transition to the counter persona, the output remains undefined. This is a result of not applying the reset to registers within the persona to reset the registers to a known state. This feature of the generated post-synthesis gate-level PR simulation model allows the output to remain an unknown (X) value until entering the known reset state.
  7. The undefined output continues throughout the counter persona, through the PR transition to the FSM persona, and through the FSM persona.
    Figure 15. Reset Sequence Simulation Waveform: Persona Registers Do Not Reset to a Known State
Level Two Title