AN 1007: Partial Reconfiguration Design Simulation Tutorial

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ID 819958
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration Design Simulation Tutorial Introduction 2. Partial Reconfiguration Simulation Overview 3. Partial Reconfiguration Simulation Capabilities 4. Types of Verification Achievable Through Simulation 5. Partial Reconfiguration Simulation Requirements 6. Partial Reconfiguration Simulation Reference Design Requirements 7. Partial Reconfiguration Simulation Reference Design Overview 8. Partial Reconfiguration Simulation Reference Design Files 9. PR Simulation Reference Design Walkthrough 10. PR Simulation Results 11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial
9. PR Simulation Reference Design Walkthrough x
9.1. Step 1: Getting Started 9.2. Step 2: Creating a Project Revision for PR Simulation 9.3. Step 3: Adding RTL Design Files to the pr_sim Revision 9.4. Step 4: Adding PR Simulation Design Files to the pr_sim Revision 9.5. Step 5: Generating Gate-level PR Simulation Models for the Persona 9.6. Step 6: Preparing the Setup Simulation Script 9.7. Step 7: Run PR Simulation
10. PR Simulation Results x
10.1. Persona Swapping Simulation 10.2. Reset Sequence Simulation 10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL
1. Partial Reconfiguration Design Simulation Tutorial Introduction
2. Partial Reconfiguration Simulation Overview
3. Partial Reconfiguration Simulation Capabilities
4. Types of Verification Achievable Through Simulation
5. Partial Reconfiguration Simulation Requirements
6. Partial Reconfiguration Simulation Reference Design Requirements
7. Partial Reconfiguration Simulation Reference Design Overview
8. Partial Reconfiguration Simulation Reference Design Files
9. PR Simulation Reference Design Walkthrough
10. PR Simulation Results
11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial

7. Partial Reconfiguration Simulation Reference Design Overview

The reference design illustrates RTL and partial reconfiguration (PR) simulations in the Questa simulation software. It implements three PR personas inside a PR region. You can swap out the persona in the FPGA by using the partial reconfiguration process.

The personas in the reference design are as follows

  • An AND gate
  • A counter
  • A finite state machine (FSM)
Each of these personas has a 100 MHz clock, an active low reset, two 1-bit inputs and one 2-bit output.
Figure 6. Partial Reconfiguration Reference Design Base Revision Block Diagram


The following figure shows the PR simulation design architecture. You can simulate the partial reconfiguration event by using simulation multiplexers on the input and output of the personas. These multiplexers are used to change which persona drives logic inside the PR region during simulation.
Figure 7. PR Simulation Design Block Diagram


The PR Simulation Wrapper is the main component of the simulation design. It contains instantiations of the gate-level PR simulation model of each persona, PR input and output multiplexers, and freeze logic controller module.

Simulation only signals PR Activate, Persona Select and Freeze do not pass through the Top Simulation Module, but rather pass directly from the Testbench to the PR Simulation Wrapper. This technique is required because the testbench and simulation wrapper are not synthesizable, while the RTL top-level modules and personas are synthesizable in a real design scenario. The Testbench controls the signals as they pass through to the PR Simulation Wrapper directly using a relative path.

You can use the PR output MUX to output unknown values (X), when PR is active, to verify that unknown values exiting the PR region do not propagate into the static region. The unknown (X) outputs of the PR persona allow you to verify your freeze strategy.

You can trigger the PR simulation register model to show unknown (X) value in all registers of the persona. This technique allows you to validate the reset sequence by showing that all registers return to a known state after PR completes and you apply reset.

The RTL simulation as well as the PR simulation (with gate-level PR simulation model of the personas), both use the same Testbench and PR Simulation Wrapper.

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