AN 1007: Partial Reconfiguration Design Simulation Tutorial

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ID 819958
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration Design Simulation Tutorial Introduction 2. Partial Reconfiguration Simulation Overview 3. Partial Reconfiguration Simulation Capabilities 4. Types of Verification Achievable Through Simulation 5. Partial Reconfiguration Simulation Requirements 6. Partial Reconfiguration Simulation Reference Design Requirements 7. Partial Reconfiguration Simulation Reference Design Overview 8. Partial Reconfiguration Simulation Reference Design Files 9. PR Simulation Reference Design Walkthrough 10. PR Simulation Results 11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial
9. PR Simulation Reference Design Walkthrough x
9.1. Step 1: Getting Started 9.2. Step 2: Creating a Project Revision for PR Simulation 9.3. Step 3: Adding RTL Design Files to the pr_sim Revision 9.4. Step 4: Adding PR Simulation Design Files to the pr_sim Revision 9.5. Step 5: Generating Gate-level PR Simulation Models for the Persona 9.6. Step 6: Preparing the Setup Simulation Script 9.7. Step 7: Run PR Simulation
10. PR Simulation Results x
10.1. Persona Swapping Simulation 10.2. Reset Sequence Simulation 10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL
1. Partial Reconfiguration Design Simulation Tutorial Introduction
2. Partial Reconfiguration Simulation Overview
3. Partial Reconfiguration Simulation Capabilities
4. Types of Verification Achievable Through Simulation
5. Partial Reconfiguration Simulation Requirements
6. Partial Reconfiguration Simulation Reference Design Requirements
7. Partial Reconfiguration Simulation Reference Design Overview
8. Partial Reconfiguration Simulation Reference Design Files
9. PR Simulation Reference Design Walkthrough
10. PR Simulation Results
11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial

10.1. Persona Swapping Simulation

Persona swapping simulation verifies the swapping of PR personas for a given PR partition. For this simulation you can use RTL or gate level PR simulation model of the personas. The simulation requires PR input and output multiplexers to specify the active persona. The testbench sequence to run this simulation is as follows:
  • Assert the pr_activate signal, while changing the persona_select signal on the PR input and output multiplexer select lines to select the desired persona.
  • After finishing PR, the testbench deasserts the pr_activate signal.
  • Reset the persona.

Refer to the pr_sim_wrapper.sv file for information on how to instantiate the PR multiplexers. The simulation library for these multiplexers is in altera_lnsim.sv.

The simulation steps are as follows:

  1. Initialization and Initial Reset occur within the first two cycles and transitions to Section #1: PR with Freeze, then reset.
  2. The two 1-bit inputs, a and b, toggle through their four possible states, and the AND gate gives the correct response on the result output signal.
  3. A PR transition occurs by activating the pr_activate signal and changing the persona_select to the counter persona. While this transition occurs, the freeze signal activates to assert the output to a known value of 1.

    When PR is complete, after one cycle in this case, the rst_n reset signal asserts to reset the counter persona to a known value state.

    For the reset to take effect, you may have to hold the freeze and rst_n signals for a longer period, depending on the persona pipeline depth delay. In this design example, each persona has a one cycle delay from input to output.

  4. The 2-bit counter counts until the next PR transition occurs. The counter undergoes the same process as step 3 when transitioning to the FSM persona.
  5. The inputs a and b toggle through its four possible states, and the FSM outputs the correct response while activated.
Figure 13. Persona Swapping Simulation Waveform
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