AN 1007: Partial Reconfiguration Design Simulation Tutorial

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ID 819958
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration Design Simulation Tutorial Introduction 2. Partial Reconfiguration Simulation Overview 3. Partial Reconfiguration Simulation Capabilities 4. Types of Verification Achievable Through Simulation 5. Partial Reconfiguration Simulation Requirements 6. Partial Reconfiguration Simulation Reference Design Requirements 7. Partial Reconfiguration Simulation Reference Design Overview 8. Partial Reconfiguration Simulation Reference Design Files 9. PR Simulation Reference Design Walkthrough 10. PR Simulation Results 11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial
9. PR Simulation Reference Design Walkthrough x
9.1. Step 1: Getting Started 9.2. Step 2: Creating a Project Revision for PR Simulation 9.3. Step 3: Adding RTL Design Files to the pr_sim Revision 9.4. Step 4: Adding PR Simulation Design Files to the pr_sim Revision 9.5. Step 5: Generating Gate-level PR Simulation Models for the Persona 9.6. Step 6: Preparing the Setup Simulation Script 9.7. Step 7: Run PR Simulation
10. PR Simulation Results x
10.1. Persona Swapping Simulation 10.2. Reset Sequence Simulation 10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL
1. Partial Reconfiguration Design Simulation Tutorial Introduction
2. Partial Reconfiguration Simulation Overview
3. Partial Reconfiguration Simulation Capabilities
4. Types of Verification Achievable Through Simulation
5. Partial Reconfiguration Simulation Requirements
6. Partial Reconfiguration Simulation Reference Design Requirements
7. Partial Reconfiguration Simulation Reference Design Overview
8. Partial Reconfiguration Simulation Reference Design Files
9. PR Simulation Reference Design Walkthrough
10. PR Simulation Results
11. Document Revision History for AN 1007: Partial Reconfiguration Design Simulation Tutorial

10.3. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL

Along with the top_sim testbench simulation, the RTL personas and PR simulation model of the personas are additional testbench subsections of interest for demonstrative purposes only. These subsections demonstrate the differences between the PR simulation model and the RTL code.

Each testbench subsection displays the output of each of the personas using either the PR simulation models (generated earlier) or the RTL. The main differences in the use of the personas are when PR transactions occur, as the following figure illustrates:
Figure 16. Persona using Post-Synthesis Gate-Level PR Simulation Model vs RTL

When the first PR transition occurs in Section #1: PR with Freeze, then reset, there is a difference in the output of the PR simulation model and RTL persona simulations. This is a feature of the PR simulation model to set all the registers in the persona to an undefined state (or X) during a PR transition. Conversely, the RTL holds the value during this time.

While use of the RTL for simulation can be familiar and convenient, the implemented PR simulation models more closely emulate the behavior of the hardware during actual PR transitions.

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