GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 8/04/2025
Public
Document Table of Contents

9.2. Design Example Components

Figure 76. Design Example Block Diagram for Multi IP Core instantiation
The GTS Ethernet Hard IP design example includes the following components:
Design Component Description
GTS Ethernet Hard IP Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate, Compile, and Validate (MAC+PCS) - Single Instance.
GTS System PLL Clocks IP Provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP .
GTS Reset Sequencer IP Provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP .
Packet Client Generates traffic pattern for MAC mode and non-MAC modes.
Avalon® Memory-Mapped Interface Decoder Decodes the Avalon® memory-mapped interface address.