GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 8/04/2025
Public
Document Table of Contents

12.2. Troubleshoot the Reset Sequence

The following section outlines the reset process steps, which are illustrated in a flow chart that explains the sequence of reset actions. Each state in the flow chart, along with its corresponding tx_lane_current and rx_lane_current_state, provides you with precise insights into the reset process, facilitating easier debugging if needed.