GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 8/04/2025
Public
Document Table of Contents

13.4.4. Reference Time Interval

Table below displays the number of bits between two subsequent reference time captures. The UI adjustment calculation uses these numbers. To speed up the simulation, the number for simulation is smaller.
Table 67.  Reference Time (TAM) Interval
FEC type:
  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL108: IEEE 802.3 RS (528,514) (CL108)
Speed FEC Type Simulation (bit) Hardware (bit)
TX RX 20 TX RX
10GE No FEC 168,960 168,960 5,406,720 168,960
25GE No FEC 168,960 168,960 5,406,720 168,960
CL74
CL108 168,960 168,960 5,406,720 5,406,720
20 Depends on the link partner AM. The numbers assume serial loopback.