GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 8/04/2025
Public
Document Table of Contents

15. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.08.04 25.1.1 Made the following changes:
  • Added HVIO acronyms in Acronyms section.
  • Updated the GTS Ethernet Hard IP Parameters: IP tab to include the Use HVIO PLL Parameter in the IP tab display.
  • Updated the Enable IEEE 1588 PTP parameter description in the Configure GTS Ethernet Hard IP section.
  • Added the following new parameters in the GTS Ethernet Hard IP Parameters: IP tab table:
    • Use HVIO PLL
    • Additional IPG removed per AM period
    • Added footnote for the 25G-1 Ethernet Mode parameter.
  • Updated Analog Parameters GUI in Analog Parameters Options section.
  • Updated the IEEE 802.3 RS(528,514) FEC support for 25GE to clause 108 instead of clause 91 as mentioned in all previous versions.
  • Added a new parameter Selects value of RX termination mode in the GTS PMA Analog Parameter Settings table.
  • Updated the Implement Required Clocking section.
  • Removed MAC from the Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode) chapter title.
  • Added the following parameters in the IP Parameter Settings for 10GE Dynamically Reconfigurable Mode Single Instance Design Example with Optional FEC table in the Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode chapter:
    • USE HVIO PLL
    • PTP Options: Enable IEEE 1588 PTP - Disable
  • Added a new parameter Enable fast simulation in the following sections:
    • Auto-Negotiation and Link Training for General Ethernet Mode
    • Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT
    • Added link to the Agilex 5 Auto-Negotiation and Link Training for Ethernet Hard IP Register map in the Ethernet Avalon Memory-Mapped Interface Address Space section.
2025.04.07 25.1 Made the following changes:
  • Added a topic Round-Trip Latency in Overview section.
  • Updated the Resource Utilization topic to include the following IP core variation names:
    • MRIP AVST 10G NO FEC to 25G RS-FEC
    • MRIP AVST 10G FEC to 10G NO FEC
  • Updated range and description of the Ethernet Operation Mode parameter in the Configure GTS Ethernet Hard IP section.
  • Moved the following parameters from Base_Port(Port #0) > Port #0 IP Configuration > Port #0 MAC Option > P0 BasicBase to the IP Tab: General Options in the Configure GTS Ethernet Hard IP section:
    • Ready latency
    • Enable asynchronous adapter clocks
  • Added a footnote to the following tabs in the Configure GTS Ethernet Hard IP section:
    • Base_Port > Port #0 IP Configuration
    • Base_Port(Port #0) > Port #0 IP Configuration > Port #0 MAC Option > P0 BasicBase
    • Base_Port(Port #0) > Port #0 IP Configuration > Port #0 MAC Option > P0 Specialized
  • Updated the diagram HDL Generation for Synthesis and Simulation in Generate HDL for Synthesis and Simulation section.
  • Updated a Directory Structure for GTS Ethernet Hard IP Design Example diagram to add a new folder support_logic inside the hardware_test_design folder.
  • Updated Directory and File Description table in the Directory Structure.
  • Updated Analog Parameters tab in the GTS Ethernet Hard IP GUI.
  • Removed the following parameters from the GTS PMA Analog Parameter Settings table:
    • Selects value of RX termination mode
    • Enable VSR mode
  • Updated the values for the Selects value of RX onchip termination parameter under the Analog RX tab.
  • Updated the GTS Ethernet Hard IP Interfaces diagram to show o_refclk_bus_out signal.
  • Updated GTS Ethernet Hard IP Clock Signals and Clock Status diagram to show o_refclk_bus_out signal.
  • Added the clock signal o_refclk_bus_out in the Implement Required Clocking section.
  • Updated Connect to the GTS Reset Sequencer IP diagram in the Connect the GTS Reset Sequencer IP section.
  • Added a note under Example of o_rx_pause Toggling in the Connect the RX MAC Flow Control Interface section.
  • Added a new chapter Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode - MAC)
  • Added a note to the address range 0x0010_0000 - 0x0010_0054 in the Ethernet Avalon Memory-Mapped Interface Address Space section.
2024.01.23 24.3.1 Made the following changes:
  • Updated GTS Ethernet Hard IP GUI to show the Ethernet Operation Mode parameter in Configure GTS Ethernet Hard IP.
  • Added the following parameters in the GTS Ethernet Hard IP Parameters table:
    • Ethernet Operation Mode
    • MAC Use case
  • Updated the diagram and table in the Directory Structure section to show ed_debug_signals.stp file.
  • Updated the GTS Ethernet Hard IP Interfaces diagram to include a note in Integrate GTS Ethernet Hard IP into Your Application section.
  • Updated the Analog Parameters tab in the GTS Ethernet Hard IP GUI to show Enable VSR Mode parameter.
  • Added new parameter Enable VSR mode in the GTS PMA Analog Parameters Settings table.
  • Added a new topic Connect the Multirate Auto-Negotiation and Link Training under Integrate to your Application.
  • Added new parameters Ethernet Operation Mode and MAC Use case in the following sections:
    • Simulate, Compile, and Validate (MAC+PCS)- Single Instance
    • Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE)- Single Instance
    • Simulate, Compile, and Validate - Single Instance
    • Simulate and Compile PTP1588- Single Instance
    • Simulate, Compile, and Validate - Multiple Instance
  • Added the following new topics under Simulate, Compile, and Validate- Auto-Negotiation and Link Training:
    • Auto-Negotiation and Link Training for General Ethernet Mode
    • Multirate Auto-Negotiation and Link Training for Reconfigurable mode AN/LT
  • Added new parameter Enable Multirate AN/LT in the Selected IP Parameter for Auto-Negotiation and Link Training table.
  • Removed the parameter Status Clock Frequency from the Selected IP Parameter for Auto-Negotiation and Link Training table.
  • Updated the following in the Use Signal Tap Analyzer for Troubleshooting section:
    • Updated the diagram
    • Added the signal rx_lane_current_status
    • Removed the signal rx_am_lock_stp_dbg
  • Added timestamp accuracy support in advanced mode in the Features section.
2024.10.12 24.3 Made the following changes:
  • Updated Resource Utilization table.
  • Updated Supported Ethernet Protocol table in Agilex™ 5 Ethernet Hard IP Features.
  • Added Aldec Riviera-PRO* simulator support in Simulate the Design Example.
  • Updated GTS Ethernet Hard IP Interfaces block diagram in the Integrate GTS Ethernet Hard IP into Your Application.
  • Removed o_rx_am_lock port from the Connect the Status Interface.
  • Updated clock connections in PTP-Based synchronous and asynchronous operation diagrams in Implement Clock Connections in PTP-Based Design.
  • Added design example generation and simulation support for D-Series and E-Series Device Group A.
  • Updated the clock controller configurations for example designs.
  • Updated Verify the Simulation Results topic in the Simulate, Compile, and Validate (MAC+PCS) - Single Instance section.
  • Corrected the script command from chkmac_status to chkmac_stats in Run the Hardware Test.
  • Updated the Simulators Output and Waveform in the Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance section.
  • Updated Simulators Output and Waveform in the Simulate, Compile, and Validate SyncE - Single Instance design example section.
  • Updated IP parameters settings for Multiple Instance and AN/LT Design Example.
  • Added hardware support for PTP1588 design example in Simulate and Compile PTP1588 - Single Instance.
  • Updated Simulators Output in the Simulate, Compile, and Validate - Auto Negotiation and Link Training.
  • Revised the per-defined signal tap debug signals and description in the Use Signal Tap Analyzer for Troubleshooting section.
  • Added Riviera-PRO script location in the IP and design example Directory Structure.
  • Updated Byte Order on the Client Interface Channels with Preamble Pass-Through in the Appendix: Order of Ethernet Transmission.
  • Updated the Appendix section: PTP RX Flow.
2024.08.05 24.2 (patch 0.01) Made the following changes:
  • Updated Select Design parameter description in the Design Example Parameters table of Generate GTS Ethernet Hard IP Design Example section.
  • Updated Clock Connections for MAC Synchronous Operation diagram in Implement MAC Synchronous Clock Connections to Single Instance section.
  • Updated Insert Alignment Markers diagram in Insert Alignment Marker section.
  • Added the following Auto-Negotiation and Link Training sections:
    • Enable Auto-Negotiation and Link Training Parameter in the Configure GTS Ethernet Hard IP.
    • Connect the Auto-Negotiation and Link Training topic in the Integrate GTS Ethernet Hard IP into Your Application chapter.
    • Simulate, Compile, and Validate - Auto-Negotiation and Link Training.
    • Auto-Negotiation and Link Training in the Block Description chapter.
2024.07.08 24.2 Made the following changes:
  • Reorganized the document structure and content.
  • Updated the following chapters:
    • Overview
    • Install and License the GTS Ethernet Hard IP
    • Configure and Generate Ethernet Hard IP Variant
    • Integrate GTS Ethernet Hard IP into Your Application
  • Added the following design example chapters and updated their content and diagrams:
    • Simulate, Compile, and Validate (MAC+PCS) - Single Instance
    • Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance
    • Simulate, Compile, and Validate SyncE - Single Instance
    • Simulate and Compile PTP 1588 - Single Instance
    • Simulate, Compile, and Validate - Multiple Instance
  • Added a new chapter: Troubleshoot and Diagnose Issues
  • Moved the following chapters to Appendix:
    • Functional Description
    • Configuration Registers
    • Document Revision History
2024.04.01 24.1 Initial release.