GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 817676
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode) 11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 12. Troubleshoot and Diagnose Issues 13. Appendix A: Functional Description 14. Appendix B: Configuration Registers 15. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex® 5 Ethernet Portfolio and Target Applications 1.5. Agilex® 5 Ethernet Hard IP Features 1.6. GTS Ethernet Hard IP Design Flow
1.5. Agilex® 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization 1.5.4. Round-Trip Latency
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training 4.10. Connect the Multirate Auto-Negotiation and Link Training 4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer IP
4.2.2. Connect the GTS Reset Sequencer IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode) x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Verify the Simulation Results
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
11.1. Auto-Negotiation and Link Training for General Ethernet Mode 11.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT 11.3. Design Example Features 11.4. Design Example Components 11.5. Simulate the Design Example 11.6. Compile the Design Example 11.7. Validate the Design Example
11.5. Simulate the Design Example x
11.5.1. Simulation Testbench Flow 11.5.2. Simulation Output
11.7. Validate the Design Example x
11.7.1. Configure the Clocks in Hardware 11.7.2. Program the FPGA 11.7.3. Run the Hardware Test
12. Troubleshoot and Diagnose Issues x
12.1. Enable Diagnostic Lookback Modes 12.2. Troubleshoot the Reset Sequence 12.3. Use Signal Tap Analyzer for Troubleshooting
12.1. Enable Diagnostic Lookback Modes x
12.1.1. Internal Serial Loopback 12.1.2. Enable MAC Loopback 12.1.3. Enable PCS Loopback 12.1.4. Enable External Loopback 12.1.5. Packet Client Loopback
12.2. Troubleshoot the Reset Sequence x
12.2.1. Debug the Power Up Reset Sequence 12.2.2. Debug the TX Reset Entry Sequence 12.2.3. Debug the TX Reset Exit Sequence 12.2.4. Debug the RX Reset Entry Sequence 12.2.5. Debug the RX Reset Exit Sequence 12.2.6. Debug the Auto Recovery Reset Sequence
13. Appendix A: Functional Description x
13.1. Datapath Description 13.2. GTS Ethernet Hard IP MAC 13.3. PCS, OTN, and FlexE Modes 13.4. Precision Time Protocol Interface 13.5. Auto-Negotiation and Link Training
13.2. GTS Ethernet Hard IP MAC x
13.2.1. MAC TX Datapath 13.2.2. MAC RX Datapath 13.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 13.2.4. Link Fault Signaling 13.2.5. Order of Ethernet Transmission:
13.2.1. MAC TX Datapath x
13.2.1.1. Insert TX Preamble, Start, and SFD 13.2.1.2. Insert Source Address 13.2.1.3. Process Length/Type Field 13.2.1.4. Pad the Client Frame 13.2.1.5. Insert Frame Check Sequence (CRC-32) 13.2.1.6. Generate and Insert Inter-Packet Gap
13.2.2. MAC RX Datapath x
13.2.2.1. Process RX Preamble 13.2.2.2. Check RX Strict SFD 13.2.2.3. Check RX FCS 13.2.2.4. Handle RX Malformed Packet 13.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames 13.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 13.2.2.7. Inter-Packet Gap
13.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
13.2.3.1. Conditions Triggering XOFF Frame Transmission 13.2.3.2. Conditions Triggering XON Frame Transmission 13.2.3.3. Pause Control and Generation Interface 13.2.3.4. Pause Control Frame Filtering
13.3. PCS, OTN, and FlexE Modes x
13.3.1. PCS Mode 13.3.2. OTN Mode 13.3.3. FlexE Mode
13.4. Precision Time Protocol Interface x
13.4.1. Features 13.4.2. PTP User Flow 13.4.3. Make PTP UI Adjustments 13.4.4. Reference Time Interval 13.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
13.4.2. PTP User Flow x
13.4.2.1. PTP TX User Flow 13.4.2.2. PTP RX User Flow
13.4.3. Make PTP UI Adjustments x
13.4.3.1. Adjust TX UI 13.4.3.2. Adjust RX UI
14. Appendix B: Configuration Registers x
14.1. Ethernet Avalon® Memory-Mapped Interface Address Space 14.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode)
11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
12. Troubleshoot and Diagnose Issues
13. Appendix A: Functional Description
14. Appendix B: Configuration Registers
15. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

10.5.3. Run the Hardware Test

Follow these steps to test the hardware design example on the System Console:
  1. The GTS Ethernet Hard IP Dynamically Reconfigurable Mode Design Example runs the external loopback test by default, with the loopback_mode parameter set to 0.
    1. External Loopback: Before performing any hardware test, attach the QSFP28 loopback module according to the QSF pinout assignments of the respective design example.
    2. Internal Loopback: To perform an internal loopback test in hardware, set the loopback_mode parameter to 1 in the parameter.tcl file located in <design_example_dir>/hardware_test_design/hwtest/src/.
  2. The jtag_port_id parameter is set to 0 by default. To change the JTAG port ID to point to the correct Agilex™ 5 FPGA Master, modify the jtag_port_id parameter in the parameter.tcl file located in <design_example_dir>/hardware_test_design/hwtest/src/.
  3. Open Tools > System Debugging Tools > System Console or type the command: 
    system-console &
  4. In the TCl Console window, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest
  5. Type source main_10G.tcl to list the available JTAG masters:
  6. Verify that the output of the TCL script matches the output from a sample test run, shown below: 
    % source main.tcl
-----------------------------------------------------------------------
JTAG Port ID       = 0
Power Up Variant   = 10G_nofec
Start of DR test: 
Applying reset through ISSP
Wait for DR Ready....
Running External Loopback Test
Run test on startup profile (10G_nofec): 

-------- Printing PHY status ---------
--------------------------------------

 RX PHY Register Access: Checking Clock Frequencies (KHz) 

      TXCLK 		:161130  (KHZ) 
      RXCLK 		:161140  (KHZ) 

 TX PLL Lock Status        0x00000001 
 Rx Frequency Lock Status  0x00000001
 RX PCS Ready              0x1
 TX Lanes Stable           0x1
 Deskewed Status           0x0
 Link Fault Status         0x00000000
 Rx Frame Error            0x00000000
 Rx AM LOCK Condition        0x00000000 

--- Initialize PKT ROM Read address ----
--------- Sending packets... ---------
 =========================================================================
                        STATISTICS FOR BASE 0x50000 (Rx)                   
 ==========================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Rx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
 =======================================================================
                        STATISTICS FOR BASE 0x50000 (Tx)                 
 ========================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Tx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
--------------------------------------
Info: RX and TX packet counts match 
--------------------------------------
Startup Traffic test passed! 

Assert EIO reset
Wait reset ack (assert) -----
Reset acknowledged
Value from issp reset probe is 0x0 

--------------------------------------------------------
Setup DR reconfiguration: 10G_nofec -> 10G_fec
Configuring DR Profile 10G_fec....
Trigger DR interrupt
Wait for DR interrupt Ack....
DR Request acknowledged

Wait for DR reconfig to be done....
DR reconfig done, check for  DR errors
NO DR Errors found

Deassert EIO reset
Wait reset ack (deassert) -----
Reset acknowledged
Value from issp reset probe is 0xff 

Run traffic test (10G_fec): 

-------- Printing PHY status ---------
--------------------------------------

 RX PHY Register Access: Checking Clock Frequencies (KHz) 

      TXCLK 		:161140  (KHZ) 
      RXCLK 		:161130  (KHZ) 


 TX PLL Lock Status          0x00000001 

 Rx Frequency Lock Status    0x00000001
 RX PCS Ready                0x1

 TX Lanes Stable             0x1 

 Deskewed Status             0x0 
 Link Fault Status           0x00000000
 Rx Frame Error              0x00000000
 Rx AM LOCK Condition        0x1 

--- Initialize PKT ROM Read address ----
--------- Sending packets... ---------
 ============================================================================
                        STATISTICS FOR BASE 0x50000 (Rx)                     
 ============================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Rx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
 ===============================================================================
                        STATISTICS FOR BASE 0x50000 (Tx)                        
 ===============================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Tx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
--------------------------------------
Info: RX and TX packet counts match 
--------------------------------------
Traffic test passed! 
 
Assert EIO reset
Wait reset ack (assert) -----
Reset acknowledged
Value from issp reset probe is 0x0 

-----------------------------------------------------------
Setup DR reconfiguration: 10G_fec -> 10G_nofec
Configuring DR Profile 10G_nofec....
Trigger DR interrupt
Wait for DR interrupt Ack....
DR Request acknowledged

Wait for DR reconfig to be done....
DR reconfig done, check for  DR errors
NO DR Errors found

Deassert EIO reset
Wait reset ack (deassert) -----
Reset acknowledged
Value from issp reset probe is 0xff 

Run traffic test (10G_nofec): 

-------- Printing PHY status ---------
--------------------------------------

 RX PHY Register Access: Checking Clock Frequencies (KHz)
      TXCLK 		:161130  (KHZ
      RXCLK 		:161130  (KHZ

 TX PLL Lock Status          0x00000001 

 Rx Frequency Lock Status    0x00000001
 RX PCS Ready                0x1
 TX Lanes Stable             0x1
 Deskewed Status             0x0 
 Link Fault Status           0x00000000
 Rx Frame Error              0x00000000
 Rx AM LOCK Condition        0x00000000 

--- Initialize PKT ROM Read address ----
--------- Sending packets... ---------
--------------------------------------
 ================================================================================
                        STATISTICS FOR BASE 0x50000 (RX)                         
 ================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Rx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
 ===========================================================================
                        STATISTICS FOR BASE 0x50000 (TX)                     
 ============================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Tx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
Data and padding octets          : 800 
Frame octets                     : 1088 
--------------------------------------
Info: RX and TX packet counts match 
--------------------------------------
Traffic test passed! 
 
Closed JTAG Master Service
End of dr_test: 
DR Test Passed
Level Two Title