GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
817676
Date
8/04/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode)
11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
12. Troubleshoot and Diagnose Issues
13. Appendix A: Functional Description
14. Appendix B: Configuration Registers
15. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
11.1. Auto-Negotiation and Link Training for General Ethernet Mode
11.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT
11.3. Design Example Features
11.4. Design Example Components
11.5. Simulate the Design Example
11.6. Compile the Design Example
11.7. Validate the Design Example
7.2. Design Example Components
When generating a design example with SyncE, the software instantiates SyncE-enabled specific components.
Figure 68. 10GE Ethernet with SyncE enabled Design Example Block Diagram
The GTS Ethernet Hard IP design example includes the following components:
Design Component | Description |
---|---|
GTS Ethernet Hard IP | Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate, Compile, and Validate (MAC+PCS) - Single Instance. |
GTS System PLL Clocks IP | Provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP . |
GTS Reset Sequencer IP | Provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP . |
Packet Client | Generates traffic pattern for MAC mode and non-MAC modes. |
Avalon® Memory-Mapped Interface Decoder | Decodes the Avalon® memory-mapped interface address. |