GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 8/04/2025
Public
Document Table of Contents

11.4. Design Example Components

Figure 85. The GTS Ethernet Hard IP Simulation Design Example Block Diagram
The GTS Ethernet Hard IP design example includes the following components:
Design Component Description
GTS Ethernet Hard IP Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate, Compile, and Validate (MAC+PCS) - Single Instance.
Auto-Negotiation and Link Training for Ethernet IP The GTS Ethernet Hard IP instantiates this IP when Enable auto-negotiation and link training is selected.
GTS System PLL Clocks GTS Ethernet Hard IP This IP provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP .
GTS Reset Sequencer GTS Ethernet Hard IP This IP provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP .
Packet Client Generates traffic pattern for MAC mode and non-MAC modes.
Avalon® memory-mapped interface Decoder Decodes the Avalon® memory-mapped interface address.