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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Generating the EMIF Design Example with the Performance Monitor
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2.8. Generating the EMIF Design Example with the Performance Monitor
You can use the Performance Monitor (PMON) to check the performance metrics of the EMIF interface.
The Performance Monitor is a synthesizable block consisting of control and status registers that let you configure and modify the performance metrics of the EMIF Interface. The Performance Monitor allows you to measure the following performance metrics:
- Read latency
- Write latency
- Read efficiency
- Write efficiency
- Overall efficiency
- Subchannel efficiency
- Subchannel back pressure
- Expected transactions in subchannel
Figure 32. Enabling the Performance Monitor in EMIF IPs
Note: Do not run any traffic on the interface that PMON is monitoring, while you are configuring PMON. Failure to observe this restriction can result in inaccurate measurements.
To generate a design example with the Performance Monitor, follow these steps:
- When generating your design example, set the Enable Performance Monitor parameter to True. This will include the Performance Monitor FPGA IP, which allows you to measure performance on an AIX4 mainband interface.
- Open the generated design example and navigate to the Quartus® Prime Pro Edition software folder containing the design example directory:
<project_directory>/<example_design_directory>/qii/ed_synth.qpf
- Make the necessary pin assignments in the .qsf file or by using the Pin Planner and compile the design by clicking Processing > Start Compilation. This generates a .sof file, which you can configure into hardware.
- Open the System Console from the Quartus® Prime Pro Edition software by clicking Load Design.
Figure 33. Load Design
- Load the pmon_library.tcl file in the system console by entering the following command:
source pmon_library.tcl
- Load the testengine_library.tcl file in the system console by entering the following command:
source testengine_library.tcl
- Set the metric configuration on desired AXI4 performance monitors:
pmon_set_all basic_eff
- Clear the counters and internal state of all performance monitors by typing the following command:
pmon_reset_counter_data_all
- Reset the state of the drivers by typing the following command:
testengine_reset
- Run traffic over the interface by typing the following command:
testengine_run
- Read the efficiency metrics on the AXI4 performance monitor by typing:
pmon_read_all
Successful reading of performance metrics produces results similar to that shown below:Figure 34. Performance Monitor (PMON) Results