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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Generating the EMIF Design Example with the Performance Monitor
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3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
When you parameterize and generate your EMIF IP you can specify that the system create directories for simulation and synthesis file sets, and generate the file sets automatically.
If you set Simulation or Synthesis to True on the Example Design tab, the system creates a complete simulation file set, or a complete synthesis file set, or both, in accordance with your selection.