External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
ID
817394
Date
4/01/2024
Public
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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Generating the EMIF Design Example with the Performance Monitor
2.7. Compiling the Agilex™ 5 EMIF Design Example
After you have made the necessary pin assignments in the .qsf file, you can compile the design example in the Quartus® Prime software.
- Navigate to the Quartus® Prime folder containing the design example directory.
- Open the Quartus® Prime project file, (.qpf).
- To begin compilation, click Processing > Start Compilation. The successful completion of compilation generates a .sof file, which enables the design to run on hardware.