GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

1.1. Supported Features

The GTS CPRI PHY Intel® FPGA IP core supports the following features:
  • Compliant with the CPRI Specification V7.0 (2015-10-09).
  • Supports line bit rates of;
    • 1.228 Gbps
    • 2.4576 Gbps
    • 3.072 Gbps
    • 4.9152 Gbps
    • 10.1376 Gbps without RS-FEC
  • Supports deterministic latency measurement.
  • Provides register access interface to external or on-chip processor, using the Intel® Avalon® memory-mapped interconnect specification.
  • Supports Physical Medium Attachment (PMA) adaptation.
Table 1.  Available Features
CPRI Line Bit Rate (Gbps) RS-FEC Support Reference Clock (MHz) Deterministic Latency Support
1.2288 No 153.6 or 122.88 Yes
2.4576 No 153.6 or 122.88 Yes
3.072 No 153.6 or 122.88 Yes
4.9152 No 153.6 or 122.88 Yes
10.1376 Without 184.32 or 122.88 Yes
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