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Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath and PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: bir1699471098199
Ixiasoft
5.5. Status Interface for 64b/66b Line Rate
This section lists the status ports for the CPRI PHY 64b/66b line rate. Each CPRI PHY channel has its own status port.
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
o_rx_pcs_ready | 1 | Asynchronous | The IP core asserts this signal to indicate that the corresponding RX datapath is ready to receive data. The signal deasserts when i_rx_rst_n is deasserted. |
o_rx_block_lock | 1 | Asynchronous | The IP core asserts this signal to indicate that 66b block alignment has completed for the corresponding CPRI PHY channel. |
o_rx_hi_ber | 1 | Asynchronous | The IP core asserts this signal in accordance with IEEE 802.3 to indicate RX PCS is in Hi-Bit Error Rate (BER) state for the corresponding CPRI PHY channel. |
o_tx_hip_ready | 1 | Asynchronous | The IP core asserts this signal after i_tx_rst_n is asserted to indicate that the CPRI PHY has completed all internal initialization, is ready to accept reconfiguration transactions and send data. |