GTS CPRI PHY Intel® FPGA IP User Guide

ID 814577
Date 3/31/2024
Public

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5.2. Reset Signals

Each of the CPRI PHY Channels in the core has its own set of reset signals. The i_reconfig_reset port is shared.
Table 16.  Reset Signals
Port Name Width (Bits) Domain Description
i_tx_rst_n 1 Asynchronous Resets the selected TX datapath. Active low.
o_tx_rst_ack_n 1 Asynchronous TX datapath reset acknowledgement. Active low.
o_tx_ready 1 Asynchronous TX datapath is out of reset and ready.
i_rx_rst_n 1 Asynchronous Resets the selected RX datapath. Active low.
o_rx_rst_ack_n 1 Asynchronous RX datapath reset acknowledgement. Active low.
o_rx_ready 1 Asynchronous RX datapath is out of reset and ready.
i_reconfig_reset 1 i_reconfig_clk Reconfig reset. Resets the AVMM soft logics to the HIP and resets CPRI PHY soft CSR, but does not reset HIP CSRs. Active high. Must be asserted once upon power-up.
o_src_rs_req 1 i_reconfig_clk

Request signal from Soft Reset Controller (SRC) to GTS Reset Sequencer Intel FPGA IP for reset operation. Asserts when there is a request to toggle reset.

In case of reset group of more than one SRC_Lane, only Initiator SRC_Lane will request for access grant.

i_src_rs_grant 1 i_reconfig_clk

Grant signal from GTS Reset Sequencer Intel FPGA IP to SRC. Asserts when the reset request is granted by the Reset Sequencer Intel FPGA IP.