GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.10. CPRI PHY Reconfiguration Interface

Table 24.  CPRI PHY Reconfiguration Interface
Port Name Width (Bits) Domain Description
i_reconfig_cpri_addr[3:0] 4 i_reconfig_clk Address for GTS CPRI PHY CSRs in the selected channel. Using word addressing format.
i_reconfig_cpri_read 1 i_reconfig_clk Read command for GTS CPRI PHY CSRs in the selected channel.
i_reconfig_cpri_write 1 i_reconfig_clk Write command for GTS CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_readdata[31:0] 32 i_reconfig_clk Read data from reads to GTS CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_readdatavalid 1 i_reconfig_clk Read data from GTS CPRI PHY CSRs is valid in the selected channel.
i_reconfig_cpri_writedata[31:0] 32 i_reconfig_clk Data for writes to GTS CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on GTS CPRI PHY CSRs in the selected channel.
Figure 11. Writing to CPRI PHY Reconfiguration
Figure 12. Reading from CPRI PHY Reconfiguration
Level Two Title