Visible to Intel only — GUID: etr1699471543922
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath and PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: etr1699471543922
Ixiasoft
5.11. Datapath and PMA Avalon Memory-Mapped Interface
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
i_reconfig_addr | 18 | i_reconfig_clk | Address for hard CSRs. Word addressing is used. |
i_reconfig_read | 1 | i_reconfig_clk | Read command for hard CSRs. |
i_reconfig_write | 1 | i_reconfig_clk | Write command for hard CSRs. |
o_reconfig_readdata | 32 | i_reconfig_clk | Read data from hard CSRs. |
o_reconfig_readdatavalid | 1 | i_reconfig_clk | Read data from hard CSRs is valid. |
i_reconfig_writedata | 32 | i_reconfig_clk | Data for writes to hard CSRs. |
o_reconfig_waitrequest | 1 | i_reconfig_clk | Stalling signal for operations on hard CSRs. |
i_reconfig_byteenable | 4 | i_reconfig_clk | Byteenable for hard CSRs |