GTS CPRI PHY Intel® FPGA IP User Guide

ID 814577
Date 3/31/2024
Public

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Document Table of Contents

4. Functional Description

The GTS CPRI PHY Intel® FPGA IP core consists of the following modules:
  • GTS transceiver channels which consists of PMA hard logic to support CPRI and Ethernet protocols. It also contains a hard PCS block that provides 64b/66b encoding scheme for 10.1376 Gbps CPRI line rate. For more information, refer to the GTS Architecture and PMA and FEC Direct PHY IP User Guide.
  • Elastic FIFO (EFIFO)—a dual clock FIFO that matches the rate differences between the GTS hard logic and soft logic.
  • Latency measurement—a module that generates a sync pulse to measure the datapath delay of the GTS CPRI PHY Intel® FPGA IP core.
  • 8b/10b PCS—a soft PCS block that provides the 8b/10b encoding scheme for the CPRI line rates of 4.9 Gbps and below.
Figure 7. IP Block Diagram