GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.1.1. Required Clock Frequencies

Table 15.  Required Clock Frequencies
Port Name Frequency (MHz) Notes
i_reconfig_clk 100 Provides CSR access on all the Avalon® memory-mapped interfaces.
o_tx_clkout 245.76 System clock divided by 2.
o_tx_clkout2 153.6 CPRI PHY system clock times (64/66) for 10G channels.
245.76 CPRI PHY system clock for 4.9G channels.
153.6 CPRI PHY system clock for 3G channels.
122.88 CPRI PHY system clock for 2.4G channels.
61.44 CPRI PHY system clock for 1.2G channels.
o_rx_clkout

245.76

 System clock divided by 2
o_rx_clkout2 153.6 Derived from recovered clock for 10G channels.
245.76 Derived from recovered clock for 4.9G channels.
153.6 Derived from recovered clock for 3G channels.
122.88 Derived from recovered clock for 2.4G channels.
61.44 Derived from recovered clock for 1.2G channels.
i_sampling_clk 250 Sampling clock for deterministic logic from external source.
o_cdr_divclk
Note: Not applicable in 23.4 IP)
46.08

refclk = 184.32 MHz

Derived from reference clock for 10G channels (refclk/N, N=4).
38.4

refclk = 153.6 MHz

Derived from reference clock for 4.9G, 3G, 2.4G, and 1.2G channels (refclk/N, N=4).
30.7

refclk = 122.88 MHz

Derived from reference clock for 10G, 4.9G, 3G, 2.4G, and 1.2G channels (refclk/N, N=4).
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