GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.1. Clock Signals

Each CPRI PHY channel has its own pair of datapath clocks and each transceiver has its own reference clock. The reconfiguration clock is shared.
Table 12.  CPRI PHY Clock Input Signals
Signal name Width (Bits) I/O Direction Description
i_syspll_clk 1 Input System PLL Clock, to be connected to GTS System PLL Clocks Intel FPGA IP.
i_refclk_tx 1 Input TX PLL reference clock.
i_refclk_rx 1 Input RX CDR reference clock.
i_pma_cu_clk 1 Input Input clock for control unit component of GTS PMA/FEC direct PHY IP.
i_reconfig_clk 1 Input Reconfiguration clock.
i_sampling_clk 1 Input Sampling clock for deterministic latency logic.
Table 13.  Clock Source SignalsThis table lists the clock source ports for the CPRI core. The IP core provides locally generated PLL clocks and recovered clocks that can be used for the datapath.
Signal Name Width (Bits) I/O Direction Description
o_cdr_divclk 1 Output Divided clock output from CDR.
o_tx_clkout 1 Output System clock divided by 2
o_tx_clkout2 1 Output
Parallel TX clock
  • For 64B/66B PCS: running at line rate/66.
  • For 8B/10B PCS: running at line rate/20.

Hold circuits using this clock in reset until o_tx_pll_lock is high.
o_rx_clkout 1 Output System clock divided by 2.
o_rx_clkout2 1 Output Parallel RX recovered clock:
  • For 64B/66B PCS, running at line rate/66.
  • For 8B/10B PCS, running at line rate/20.

Hold circuits using this clock in reset until o_rx_cdr_lock is high.

Table 14.  Clock Status SignalsThis table lists the clock status ports for the CPRI core. Use these ports to hold the circuits that use clock sources from the IP core in reset until the PLLs driving the clocks are locked.
Signal Name Width (Bits) I/O Direction Description
o_tx_pll_lock 1 Output Indicates the TX PLL driving clock signals from the core is locked.

Do not use the o_tx_clkout or o_tx_clkout2 clocks until the o_tx_pll_lock clock is high.

o_rx_cdr_lock 1 Output Indicates that the recovered clocks are locked to data.

Do not use the o_rx_clkout or o_rx_clkout2 clocks until the o_rx_cdr_lock clock is high.

i_syspll_lock 1 Input Lock signal from GTS System PLL Clocks Intel FPGA IP, to be monitored by HIP.

Section Content
Required Clock Frequencies

Level Two Title