GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

3. IP Parameter Settings

You customize the IP core by specifying parameters in the IP parameter editor.
Figure 5. IP Parameter Editor (for 23.4 CPRI PHY Editor)
Figure 6. IP Parameter Editor
Table 7.  Parameter Settings: IP Tab
Parameter Supported Values Default Setting Description
CPRI General Options
CPRI Rate
  • 1.2288G (8b/10b)
  • 2.4576G (8b/10b)
  • 3.072G (8b/10b)
  • 4.9152G (8b/10b)
  • 10.1376G (64b/66b)
 10.1376G (64b/66b) Selects the CPRI data rate.
CPRI Core Options
System PLL Frequency 491.52 MHz 491.52 MHz Select the System PLL frequency for your IP.
Enable CDR Clock Output (only supported in CPRI PHY IP 24.1)
  • On
  • Off
 Off

Turn on this parameter to enable CDR reference clock output.

o_cdr_divclk= refclk/N

Refer to the Required Clock Frequencies on page 26 for exact values.
CPRI PMA Options
PMA Reference Frequency
  • 153.6 MHz
  • 184.32 MHz
  • 122.88 MHz
 184.32 MHz Reference clock frequency support:
  • For CPRI line rates that include 8b/10b soft PCS, use a reference clock of 153.6 MHz or 122.88 MHz.
  • For CPRI line rates that include 64b/66b hard PCS, use a reference clock of 184.32 MHz or 122.88 MHz.
Configuration, Debug, and Extension Option (for CPRI PHY IP 24.1 only)

Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface

  • On
  • Off
 Off

When turned On, the GTS CPRI PHY Intel FPGA IP core includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the Datapath and PMA interface block. It can perform certain tests and debug functions through the JTAG using the System Console. This option may require that you include a jtag_debug link in the system.

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