Visible to Intel only — GUID: mzv1699470330280
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath and PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: mzv1699470330280
Ixiasoft
4.1. Reset Logic
There are three main user accessible reset ports:
- i_tx_rst_n—resets the TX datapath.
- i_rx_rst_n—resets the RX datapath.
- i_reconfig_reset—resets the Avalon® memory-mapped interface connections to PCS + PMA CSRs, and soft IP CSR.
Figure 8. Reset Block Diagram