GTS CPRI PHY Intel® FPGA IP User Guide

ID 814577
Date 3/31/2024
Public

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Document Table of Contents

4.1. Reset Logic

There are three main user accessible reset ports:
  • i_tx_rst_n—resets the TX datapath.
  • i_rx_rst_n—resets the RX datapath.
  • i_reconfig_reset—resets the Avalon® memory-mapped interface connections to PCS + PMA CSRs, and soft IP CSR.
Figure 8. Reset Block Diagram