Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public
Document Table of Contents

4.3.1.9. set_csr for F-Tile

set_csr SAL command is an indirect CSR access to write to HSSI SS CSRs. The CSR address and write data are written into HSSI Address/Write Data CSRs respectively and then write to HSSI Command/Status CSR to trigger the write CSR operation.

Two of the examples on how the Address[25:2] field in the HSSI Control/Address CSR is determined is shown below.

Assuming user would like to access Tx MAC Link Fault Config register (for detail about register map, refer to individual Ethernet User Guide) for Agilex F-tile channel 8 (1x25GbE).

Tx MAC Link Fault Config register byte offset = 0x1200

Agilex F-tile transceiver channel 8 base address = 0x1200000 (For the base address of each F-tile channel, refer to the F-Tile Address Maps.

AXI-Lite CSR read request address = 0x1200 + 0x1200000 = 0x1201200 (byte addressing)

HSSI Control/Address CSR Address[25:2] field = 0x1201200 / 4 = 0x480480

PTP Packet Classifier registers use the same access mechanism as Ethernet Reconfig registers.

The next example shows user accesses RS-FEC e25g_s0_rsfec_top register (for details about E-tile register address map, refer to E-tile Transceiver User Guide) for Agilex F-tile channel 10 (1x50GbE segment 1).

e25g_s0_rsfec_top register byte offset = 0x64C0

Agilex F-tile transceiver channel 10 base address = 0x160_0000

AXI-Lite CSR write request address = 0x160_0000 + 0x64C0 = 0x160_64C0

HSSI Control/Address CSR Address[25:2] field = 0x160_64C0 / 4 = 0x581930

HSSI Command/Status CSR Register Offset field is ignored as the set_csr only supports 32b register access.