Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023

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5.1.1. AXI-Lite CSR

This AXI-Lite interface is synchronous to app_ss_lite_clk and its reset signal is app_ss_lite_areset_n. The interface is compliant to the AXI Standard.
Table 28.  AXI-Lite CSR Interface Signals
Signal Name Direction Description
app_ss_lite_clk In Clock signal.
app_ss_lite_araddr[25:0] In Read address.
app_ss_lite_arprot[2:0] In Read address channel privilege and security attribute.
app_ss_lite_arvalid In Read address channel valid.
app_ss_lite_awaddr[25:0] In Write address.
app_ss_lite_awprot[2:0] In Privilege and security level of the transaction.
app_ss_lite_awvalid In Write address valid.
app_ss_lite_bready In Indicates that the master can accept a write response
app_ss_lite_rready In Indicates that the master can accept the read data and response.
app_ss_lite_wdata[31:0] In Writedata.
app_ss_lite_wstrb[3:0] In Indicates the byte lanes that hold valid data.
app_ss_lite_wvalid In Write data valid.
app_ss_lite_areset_n In Asynchronous reset.
ss_app_lite_arready Out Indicates that the slave is ready to accept a read address transaction.
ss_app_lite_awready Out Indicates the slave is ready to accept a write transaction.
ss_app_lite_bresp[1:0] Out Indicates the status of the write transaction.
ss_app_lite_bvalid Out Write response valid.
ss_app_lite_rdata[31:0] Out Read data.
ss_app_lite_rresp[1:0] Out Indicates the status of the read transfer.
ss_app_lite_rvalid Out Read data valid.
ss_app_lite_wready Out Indicates that the salve can accept the write data.