Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public
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8.4.3. Steps to Run the Design Example on Hardware

Running the design in hardware:

  1. Program the device via the JTAG programmer
  2. Open a System Console session
  3. Navigate to the hwtest_sl directory for E-tile designs or the hwtest_f directory for F-tile designs.
  4. Type source main_script.tcl
  5. Observe script output

The following sample output illustrates a successful hardware test run for the Ethernet Subsystem IP core design example on E-tile.

Available JTAG Masters:
0: /devices/10M16S(A|C|L)@2#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/(110:132 v1 #0)/phy_0/master
1: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_0/hssi_ss_0_hssi_ss_dr_cpu_hssi_ss_dr_cpu_nios2_gen2_0.data_master
2: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_3/phy_0/altera_jtag_avalon_master_0.master
3: /devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_4/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_0/alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto.avalon_master

Type set_jtag # to select a master
Type list_jtag to display this list again
Currently selected master is 1:
/devices/AGFB014R24A@1#USB-1#FM6 SI|SoC devkits#PG15SWIPLAB1062.gar.corp.intel.com/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_0/hssi_ss_0_hssi_ss_dr_cpu_hssi_ss_dr_cpu_nios2_gen2_0.data_master
Info: (default) JTAG Port ID          = 2
Info: (default) Internal Serial Loopback = 1
Info: (default) Port List = 0 4 8 12
Info: (default) PTP Enable   = 0 0 0 0
Info: (default) EnhancedPTPAccuracy Enable  = 0 1 0 0
Info: (default) Speed = 100G_fec 100G_fec 100G_fec 100G
Info: (default) PCS Enabled List = 0 0 0 0
Info: (default) DR Enabled List = 0 0 0 0
Info: (default) Base Profile List = 0 0 0 0
Info: (default) Latency Measurement Enable = 0
Info: (default) Throughput Measurement Enable = 0
Info: (default) 100G PAM4 Enabled List = 1 1 1 1
Info: (default) PMA Adaptation = 0 0 0 0
Info: (default) PMAConfig Number (default)     =   0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
Info: Hotplug Enable (enable=1, disable=0) (default) : set hotplug_en     0
Info: PMA Calibration (enable=1, disable=0) (default) : set pma_calibration_en     1
ANLT Port 0 REG: 0x00000000 & anlt_en: 0

Info: Enabled internal loopback with calibration 


Info: Test <p0 c3_ehip_xcvr_loopback_test> Passed 


Info: Test <p0 c3_ehip_traffic_basic_test> Passed 

ANLT Port 4 REG: 0x00000000 & anlt_en: 0

Info: Enabled internal loopback with calibration 


Info: Test <p4 c3_ehip_xcvr_loopback_test> Passed 


Info: Test <p4 c3_ehip_traffic_basic_test> Passed 

ANLT Port 8 REG: 0x00000000 & anlt_en: 0

Info: Enabled internal loopback with calibration 


Info: Test <p8 c3_ehip_xcvr_loopback_test> Passed 


Info: Test <p8 c3_ehip_traffic_basic_test> Passed 

ANLT Port 12 REG: 0x00000000 & anlt_en: 0

Info: Enabled internal loopback with calibration 


Info: Test <p12 c3_ehip_xcvr_loopback_test> Passed 


Info: Test <p12 c3_ehip_traffic_basic_test> Passed