Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
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4.3.1.16. Reset MAC Statistics

Issuing reset MAC statistic SAL command clears statistic registers value for the specified port. The user can choose to reset either TX or RX statistics register only or reset both TX and RX statistics registers by setting bit 16 (TX) and 17 (RX) on the HSSI Control/Address Register.

For E-tile, in the event of resetting both TX and RX statistic registers, the NIOS controller writes 1 to TX_CNTR_CONFIG Register (offset 0x845) bit 0 to reset all TX statistic registers and writes 1 to RX_CNTR_CONFIG Register (offset 0x945) bit 0 to reset all RX statistic registers. After 20 clock cycles, the NIOS controller issues another write command with 0x0 to TX_CNTR_CONFIG and RX_CNTR_CONFIG registers to release the reset for TX/RX statistic registers.

For F-tile, in the event of resetting both Tx and Rx statistic registers, NIOS write 1 to CNTR_TX_CONFIG CSR (0x1274 offset) bit 0 to reset all TX statistic registers and write 1 to CNTR_RX_CONFIG CSR (0x1278 offset) bit 0 to reset all RX statistic registers. After 20 clock cycles, another write with 0x0 to CNTR_TX_CONFIG CSR and to CNTR_RX_CONFIG CSR to release the reset for TX/RX statistic registers.