Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public
Document Table of Contents

4.3.1.10. get_csr for E-Tile

get_csr SAL command is an indirect CSR access to read to the Ethernet Subsystem Registers. The CSR address is written to HSSI Control/Address CSR and then a write to the HSSI Command/Status Register is required to trigger the read CSR operation. The CSR read data is written into HSSI Read Data CSR.

ROffset field in HSSI Command/Status Register is only applicable when the user reads PMA AVMM/Capabilites registers. All other registers read disregard the value in this field.

Refer to set_csr for E-Tile example above to determine the Address[25:2] field in the HSSI Control/Address CSR for get_csr command.

The PMA AVMM/Capabilites register is per 8 bits.
  • Write HSSI Control/Address Register 0x6 (SAL get_csr Command), 0x0 (Port), 0x0 (Channel), Address[25:2] (PMA)
  • Write HSSI Command/Status Register to configure READ_CMD = 1, WRITE_CMD = 0, ROffset = 0 - 3 (Address[1:0])
  • Read HSSI Command/Status Register ACK_TRANS, BUSY and ERROR.
  • If ACK_TRANS = 1 and BUSY/ERROR = 0
  • Read HSSI Read Data [7:0] for 8 bits PMA AVMM/Capabilities register data
  • Write 0x0 to clear HSSI Command/Status and HSSI Control/Address
The read rate of RS-FEC registers is per 32 bits.
  • Write HSSI Control/Address Register 0x6 (SAL get_csr Command), 0x0 (Port), 0x0 (Channel), Address[25:2] (RS-FEC registers address)
  • Write HSSI Command/Status Register to configure READ_CMD = 1, WRITE_CMD = 0, ROffset = 0 (ignored)
    • Internally, the subsystem generates 4 x 8 bit RS-FEC register reads
    • Each 8-bit RS-FEC register read is separated by 10us (when the AXI-Lite clock is 125MHz) or 12.5us (when the AXI-Lite frequency is 100MHz)
  • Read HSSI Command/Status Register ACK_TRANS, BUSY and ERROR
  • If ACK_TRANS = 1 and BUSY/ERROR = 0
  • Read HSSI Read Data [31:0]
  • Write 0x0 to clear HSSI Command/Status and HSSI Control/Address