Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023

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Document Table of Contents

7.1.19. Priority Flow Control RX Queue Threshold

Description: PFC RX Queue high and low thresholds

Byte Offset: 0x4080 + 4 x (0 - 7

Addressing Mode: 32 bits

Bit Type Reset Description
31:14 RO 0 Reserved
13:8 RW 0b000011


Sets the high threshold for RX Queue

High threshold for RX Queue = 128 x cfg_rx_high_th[Q]

7:6 RO 0 Reserved
5:0 RW 0b00010 cfg_rx_low_th[Q]

Sets the low threshold for RX Queue

Low threshold for RX Queue = 128 x cfg_rx_low_th[Q]