Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public

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Document Table of Contents

7.4. F-Tile ANLT Port Register Map

Table 53.  F-Tile ANLT Port Register Addresses
Port Start Address End Address
0 0x10000 0x103FF
1 0x10400 0x107FF
2 0x10800 0x10BFF
3 0x10C00 0x10FFF
4 0x11000 0x113FF
5 0x11400 0x117FF
6 0x11800 0x11BFF
7 0x11C00 0x11FFF
8 0x12000 0x123FF
9 0x12400 0x127FF
10 0x12800 0x12BFF
11 0x12C00 0x12FFF
12 0x13000 0x133FF
13 0x13400 0x137FF
14 0x13800 0x13BFF
15 0x13C00 0x13FFF
16 0x14000 0x143FF
17 0x14400 0x147FF
18 0x14800 0x14BFF
19 0x14C00 0x14FFF