Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
Public

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4.1. AXI Stream Bridge

This bridge is responsible for converting the AXI-ST Data of the user interface to the AVST data interface of the underlying IP modules, and vice versa. The AVST interface supports both SOP aligned and MAC segmented Client Interfaces while the AXI-ST interface supports both Single and Multi Packet Modes. The bridge also supports single MAC segmented interface converted to multiple streams of AXI-ST Single packet mode and vice versa.

The AXI bridge is responsible for converting between these interfaces based on the table below.

Speed AVST Data Width AVST Freq(MHz) AXI-ST Data Width AXI Packet Mode Freq(MHz) Number of Streams
10G 64 SOP 161.13 64 Single 415.03 1
64 Segment 161.13 64 Multi 161.13 1
25G 64 SOP 402.83/415.03 64 Single 402.83/415.03 1
64 Segment 402.83/415.03 64 Multi 402.83/415.03 1
40G/50G 128 SOP 402.83/415.03 128 Single 402.83/415.03 1
128 SOP with preamble passthrough 402.83/415.03 256 Single 402.83/415.03 1
128 Segment 402.83/415.03 128 Multi 402.83/415.03 1
100G 512 SOP 402.83/415.03 512 Single 402.83/415.03 1
256 Segment 402.83/415.03 256 Multi 402.83/415.03 1
200G 512 Segment 402.83/415.03 512 Multi 402.83/415.03 1
512 Segment 402.83/415.03 5122 Single 402.83/415.03 2
400G 1024 Segment 402.83/415.03 1024 Multi 402.83/415.03 1
1024 Segment 402.83/415.03 10242 Single 402.83/415.03 2
Note: When Enable System PLL for F-Tile parameter is enabled, the F-Tile system PLL IP is integrated into the Ethernet Subsystem IP and configured to 830.07MHz. Additionally, the AXI-ST clocks will be configured to 415.03MHz for all Ethernet speeds from 10GE to 400GE.
2 The highlighted configurations are supported through multi stream mode, which converts a single MAC segmented interface into multiple streams of lower data width buses.