Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
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4.3.1.7. get_mtu

Issuing get_mtu SAL command triggers two CSR read operations to read out Maximum TX frame size register (E-Tile offset 0x407/F-Tile offset 0x1208 ) value and RX frame size Register (E-Tile offset 506/F-Tile offset 0x121C). The lower 16-bit of HSSI Read Data Register is populated with 16 bits of Maximum TX frame size; the upper 16-bit is populated with 16 bits of Maximum RX frame size.

Table 24.   get_mtu bit description
HSSI Read Data CSR [31:16] Maximum TX frame size
HSSI Read Data CSR [15:0] Maximum RX frame size