Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 12/08/2023
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2.2. Supported Features

The IP core handles the frame encapsulation and flow of data between client logic and an Ethernet network through 10Gbps, 25Gbps, 40Gbps, 50Gbps, 100Gbps, 200Gbps and 400Gbps Ethernet PHY with optional Forward Error Correction (FEC). The client data interface is implemented on AXI4-Streaming interface and AXI4-Lite interface for register access.
Table 7.  Supported Ethernet Protocols
Ethernet Channel Tile Support Supported Ports per Subsystem Protocol Lanes FEC PTP AN/LT
10GbE E, F 1-16 10GBASE-KR 1x10.3125 Gbps NRZ lane for Copper Backplane N Y Y1
E, F 1-16 10GBASE-CR 1x10.3125 Gbps NRZ lane for Direct Attach Copper Cable N Y 1 Y1
E, F 1-16 10GBASE-R 1x10.3125 Gbps NRZ lane for Low Loss Connections to External PHY Modules N Y1 Y1
25GbE E, F 1-16 25GBASE-KR 1x25.78125 Gbps NRZ lane for Copper Backplane RSFEC Y1 Y1
E, F 1-16 25GBASE-CR 1x25.78125 Gbps NRZ lane for Direct Attach Copper Cable RSFEC Y1 Y1
E, F 1-16

25GBASE-R AUI

1x25.78125 Gbps NRZ lane for Low Loss Connections to External PHY Modules RSFEC Y1 Y1
E, F 1-16

25GBASE-R Consortium Link

1x25.78125 Gbps NRZ lane based on the 25G/50G Consortium Specification RSFEC Y1 Y1
40GbE F only 1-4 40GBASE-KR4 4x10.3125 Gbps NRZ lane for Copper Backplane N N Y
F only 1-4 40GBASE-CR4 4x10.3125Gbps NRZ lane for Direct Attach Copper Cable N N Y
F only 1-4 40GBASE-SR4 4x10.3125Gbps NRZ for optical fiber N N Y
50GbE F only 1-8 50GBASE-KR2 2x25.78125Gbps NRZ for Copper Backplane RSFEC Y Y
F only 1-8 50GBASE-CR2 2x25.78125Gbps NRZ for Direct Attach Copper Cable RSFEC Y Y
F only 1-8 50GAUI-2 2x25.78125Gbps NRZ lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module RSFEC Y Y
F only 1-8 50GAUI-1 1x53.125 Gbps PAM4 KPFEC, ETC Y Y
100GbE E, F 1-4

100GBASE-KR4

4x25.78125 Gbps Non-Return-to-Zero (NRZ) lanes for Copper Backplane RSFEC Y Y
E, F 1-4

100GBASE-CR4

4x25.78125 Gbps NRZ lanes for Direct Attach Copper Cable RSFEC Y Y
E, F 1-4 CAUI-4

4x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module

RSFEC Y Y
E, F 1-4 CAUI-2 2x53.125Gbps PAM4 KPFEC, ETC Y Y
F only 1-4 CAUI-1 1x106.25Gbps PAM4 KPFEC Y Y
200GbE F only 1-2 200GAUI-4 4x53.125 Gbps PAM4 KPFEC, ETC Y Y
F only 1-2 200GAUI-2 2x106.25 Gbps PAM4 KPFEC Y Y
F only 1-2 200GAUI-8 8x25.78125 Gbps PAM4 KPFEC Y Y
400GbE F only 1 400GAUI-8 8x53.125 Gbps PAM4 KPFEC, ETC Y Y
F only 1 400GAUI-4 4x106.24 Gbps Gbps PAM4 KPFEC Y Y
Table 8.  Supported CPRI Protocols
CPRI Channel Tile Support Supported Ports per Subsystem Protocol Lanes RSFEC
2.4G_PMA E 1-16 CPRI 1x2.4G N
4.9G_PMA E 1-16 CPRI 1x4.9G N
9.8G_PMA E 1-16 CPRI 1x9.8G N
10.1G_PCS E 1-16 CPRI 1x10.1G Y
12.2G_PCS E 1-16 CPRI 1x12.2G Y
24.3G_PCS E 1-16 CPRI 1x24.3G Y
1 For E-Tile, when AN/LT is enabled, PTP cannot be enabled for multi-port 10GbE and 25GbE design.