Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 1/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status 7.1.21. HSSI Hotplug Debug Port Control 7.1.22. HSSI Hotplug Debug Port Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3.1.8. set_csr for E-Tile

set_csr SAL command is an indirect CSR access to write to registers of the Ethernet Subsystem. The CSR address and write data are written into the HSSI Control/Address Register and the Write Data Register respectively. Then, a write to the HSSI Command/Status CSR is required to trigger the write CSR operation.

For base addresses, refer to Register Descriptions.

For register map of E-tile Hard IP for Ethernet Hard IP, refer to Port Registers.

The table below shows the E-tile CSR address mapping (Refer to the Register Description of E-Tile Ethernet Hard IP User Guide) for channel 0. Except for the difference in base address, which is specified in the Register Map section, the CSR address mapping for different channels have the same word/byte offset as indicated in the table below. For example, channel 0's base address is 0x020_0000, while channel 8 base address is 0x120_0000. You need to multiply the register address in word offset by four then add the base address of the channel to obtain the CSR address on that channel. If the CSR address is in byte offset (for example PTP registers), the offset is directly added to base address without multiplication. To access these registers, use the set_csr SAL command to write bit [25:2] of the calculated address to the HSSI Control/Address Register.
Table 30.  E-Tile CSR Address
Base Address Word/Byte Offset Description
Channel 0
0x020_0000 (EHIPLANE/EHIPCORE – Ethernet Reconfiguration) (Word offset) 0x0B0-0x0E8 Auto Negotiation and Link Training registers
0x300-0x3FF PHY registers
0x310-0x310 Reset Controller registers (E-Tile)
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x7FF Pause and Priority- Based Flow Control registers
0x800-0x8FF TX Statistics Counter registers
0x900-0x9FF RX Statistics Counter registers
0xA00-0xAFF TX 1588 PTP registers
0xB00-0xBFF RX 1588 PTP registers
0x020_4000 (RS-FEC – RS-FEC Reconfiguration) (Byte offset) 0x000-0x2FF TX and RX RS-FEC registers
0x024_0000 (PHY – XCVR Reconfiguration) (Byte offset) 0x000-0x144 PMA Capability registers (0x40000-0x40144)
0x025_0000 (PHY – XCVR Reconfiguration) (Byte offset) 0x000-0x207 PMA AVMM registers
0x026_0000 N/A Soft IPs (MAC, PCS)
0x026_1000 (Byte offset) Parser registers offset (Byte offset) PTP Packet Classifier
0x026_2000 — Reserved

The following example shows how the Address[25:2] field in the HSSI Control/Address CSR is determined (Please refer to the specific Ethernet User Guide for a detailed register map).

TX MAC Link Fault Configuration register word offset = 0x405

The E-Tile transceiver channel 8 base address = 0x1200000 (Refer to the base address of each E-tile channel).

AXI-Lite CSR read request address = 0x405*4 + 0x120_0000 = 0x120_1014 (byte addressing).

PTP Packet Classifier Registers use the same access mechanism as Ethernet Reconfiguration Registers.

The following example illustrates a user accessing the RS-FEC rsfec_top_tx_cfg register (For the detailed register address map, refer to the E-Tile Transceiver User Guide) for E-Tile channel 10.
  • rsfec_top_tx_cfg register byte offset = 0x10
  • The E-Tile transceiver channel 10 base address = 0x160_4000
  • AXI-Lite CSR write request address = 0x160_4000 + 0x10 = 0x160_4010 (depending on write strobe, a single AX-Lite write can create up to four single-byte write access.
  • AXI-Lite CSR write request address = 0x160_4000 + 0x10 = 0x160_4010 (depending on write strobe, a single AX-Lite write can create up to four single-byte write access.
  • AXI-Lite CSR read request address = 0x160_4000 + 0x10 = 0x160_4010 (a single AXI-Lite read can generate four single byte read accesses to the RS-FEC reconfiguration interface. For example, read 1B from 0x160_4010, read 1B from 0x160_4011, read 1B from 0x160_4012, read 1B from 0x160_4013, and return all 32b through AXI-Lite in single request.
  • HSSI Control/Address CSR Address[25:2] field = 0x160_4010 / 4 = 0x58100.
  • PMA AVMM and capability registers use the same access mechanism as RS-FEC registers. These registers are internally routed to XCVR Reconfiguration interface or PTP XCVR Reconfiguration interface depending on the channel number.
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