Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 1/23/2024
Public
Document Table of Contents

7.6. F-Tile DR Controller Register Map

The F-Tile Dynamic Reconfiguration (DR) Controller registers are mapped to the subsystem CSR space.
Table 60.  F-Tile Dynamic Reconfiguration Controller Register Addresses
Reconfiguration Interface Address
Dynamic Reconfiguration Controller Byte Offset: 0x60000 - 0x603FF