High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS*

You can simulate your HBM2E IP using Synopsys* VCS* software.
  1. Navigate to the <project_directory>/<design_example_directory>/sim/ed_sim/synopsys/vcs directory.
  2. To run the simulation, type sh vcs_setup.sh. The simulation stops once the traffic generator test completes successfully.
  3. To generate simulation results with the waveform, type sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+dumpvars+test.vpd".
  4. To view the waveform, type dve & to launch the waveform viewer. Add the necessary signals or module to the waveform view to view the required signals.